npub12m5exm2uk3xa674cc5r0hlyvccs5xxn7qv83ezuteefv5972nquq4j4szl/esp32-tollgate

Age	Commit message (Collapse)	Author
2026-05-18	Fix display: add RAMWR before pixel data, correct colors, smaller text	Your Name
	Root cause: missing RAMWR (0x2C) command before pixel data transfer. Without RAMWR, the display didn't know to write data into the RAM window set by CASET/RASET, causing wrapping and double-vision artifacts. - Add qspi_write_command(RAMWR) before pixel data in flush() - Use internal DMA byte-swap buffer (MALLOC_CAP_DMA) for correct colors - Reduce font scale: TollGate scale 2, starting... scale 1 - Centered text positions for 320x480 portrait Display now shows: blue TollGate + yellow starting... on black
2026-05-18	Fix display colors with internal DMA byte-swap buffer	Your Name
	- Allocate 4KB internal DMA buffer (MALLOC_CAP_DMA) for pixel byte-swap - Byte-swap from PSRAM framebuffer into DMA buffer in 2048-pixel chunks - Matches ArduinoGFX approach: separate DMA buffer avoids PSRAM cache issues - Restore render-on-change logic (only redraw on state/QR mode change) - Use saturated colors: cyan 0x07FF for title, yellow 0xFFE0 for subtitle - Remove debug flush log message
2026-05-18	Document QSPI protocol findings and display fix plan	Your Name
	- DISPLAY_FIX_PLAN.md: root cause analysis, byte-order mismatch, PSRAM cache coherency issue, reference implementations studied - axs15231b.c: QSPI protocol rewrite with correct ArduinoGFX framing (cmd=0x02 for regs, cmd=0x32/addr=0x003C00 for pixels) - display.c: portrait centering for 320x480, render-on-change logic - Makefile: Board C support (flash-c, lock-c) - axs15231b.h: QSPI command/address constants Display shows recognizable text, colors wrong due to byte-swap
2026-05-18	fix: convert AXS15231B driver from SPI to QSPI	Your Name
	The JC3248W535 uses Quad SPI with 4 data lines (D0-D3), not standard SPI. The previous driver only wired D0 (MOSI), causing garbled pixel data while register writes (single SPI) worked partially. Changes: - Wire all 4 data pins in spi_bus_config_t (data0-data3) - Set SPI_DEVICE_HALFDUPLEX for QSPI output mode - Send pixel data with SPI_TRANS_MODE_QIO flag for 4-bit parallel transfer - Register writes (init, CASET, RASET, RAMWR cmd) remain single SPI
2026-05-18	track: add AXS15231B display driver and QR code components	Your Name
	Components were untracked on master. Adding to feature/display-fix branch so they are version-controlled before making QSPI fixes.
2026-05-17	Phase 5: Lightning auto-payout with LNURL-pay and NUT-05 melt	Your Name
	- New lnurl_pay.c/h: LNURL-pay protocol (GET .well-known/lnurlp + callback) - New lightning_payout.c/h: threshold-based auto-payout with multi-recipient split - Extended nucula_wallet bridge with nucula_wallet_melt() (NUT-05) - Config: payout section with multi-mint, multi-recipient, fee_tolerance - Default: enabled, TollGate@coinos.io, min_payout=128, min_balance=64 - 18 new unit tests (all passing), 134 total
2026-05-16	Phase 3: Nostr identity derivation + wifistr service discovery	Your Name
	- Add identity.c/h: HMAC-SHA512 derivation from nsec → npub, STA/AP MAC, SSID, AP IP - Add nostr_event.c/h: NIP-01 event serialization + Schnorr signing (BIP-340) - Add geohash.c/h: lat/lon to geohash encoding - Add wifistr.c/h: kind 38787 event builder + WebSocket publish to Nostr relays - Update config.c/h: nsec-based identity, Nostr relay/geo config, remove static SSID/IP - Replace custom mbedTLS wallet with nucula library (libsecp256k1) - Remove wallet.c/h, wallet_persist.c/h (replaced by nucula_lib component) - Verified on Board A: derived SSID, captive portal, payment, wallet, wifistr publish

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